We are looking for a motivated Physical Design and Timing Engineer – Intern to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, join us today!
What you’ll be doing:
- Drive physical design, power, and timing closure for high-frequency and low-power designs.
- Help drive frontend and backend implementation in select areas, from RTL to GDSII.
- Run physical design experiments and help develop flows and methodologies.
What we need to see:
- Pursuing an MS or Ph.D. in Electrical or Computer Engineering.
- Familiarity with applying AI/ML techniques to physical design workflows to accelerate design, analysis, or automation tasks.
- Knowledge of or experience with Static Timing Analysis (STA), power analysis, and power reduction.
- Some experience in logic synthesis and equivalence checking.
- Experience with physical optimization, e.g., placement, routing, clock tree, etc.
- Some background in industry-standard EDA tools (e.g., Cadence, Synopsys, Siemens, etc.).
- Proficiency in programming and scripting languages such as Perl, Tcl, Make, Python, etc.
For more details, visit their website. To apply, click here.
Published on October 2nd, 2026Last updated on October 2nd, 2026